1. Field of the Invention
This invention relates to rectifier circuits and more particularly to a CMOS half wave and full wave rectifier circuit.
2. Description of the Prior Art
Under a number of circumstances, it is desirable to provide a CMOS rectifier circuit on a common substrate with other circuitry, however this can result in the problem of current injection from the rectifier into the substrate, resulting in latch-up of the attached circuitry and the destruction of other semiconductor devices included on the same substrate. The latch-up problem can occur on startup, that is beginning the cycle with no input to the rectifier circuit and no output being provided by the rectifier circuit. During the charging o the typical filter capacitor to bring the output voltage up to the desired level, injection of current into the substrate can cause the aforementioned latch-up problem. Secondly, when excessive input current is applied to in prior art circuitry, the current becomes so large that it forward biases the drain to substrate diode which turns on the inherent parasitic bipolar transistor resulting in the injection of current into the substrate, which can destroy other semiconductor devices sharing a common substrate. Also, with typical prior art rectifier circuits, which will be described more fully hereinafter, on startup a certain amount of current is shunted around the field effect transistor and is not passed through the rectifying diode to charge the filter capacitor to bring it up to the desired output voltage and this undesired shunting of current results in a delay in charging the filter capacitor to the desired output level.
A typical field effect transistor in full wave rectifier of the type utilized in the prior art is utilized in FIG. 1. FIG. 2 illustrates one half of the full wave rectifier of FIG. 1, and will be used to illustrate the typical problems involved in prior art rectifier circuits, including the shunting of current around the principal conducting path because of the parasitic bipolar device inherent in field effect transistors.
Referring to FIG. 1, full wave rectifier circuit 1 is illustrated and includes input terminals AC1 and AC2 for receiving an alternating current input signal to be rectified by the circuitry and provide DC+ and DC- output voltage at output terminals 2 and 3 respectively. Included in full wave rectifier circuit 1 are a P-channel field effect transistor P1 and a P-channel field effect transistor P2, each of which includes a drain, source, gate, and body as illustrated in FIG. 1.
The gate of field effect transistor P2 is connected to input terminal AC1 by conductor 4 and the gate of field effect transistor P1 is connected to input terminal AC2 by conductor 5. The source of field effect transistor P1 is connected to the positive output terminal 2 by conductor 6, and the source of field effect transistor P2 is also connected to conductor 6. The drain of field effect transistor P1 is connected to conductor 4 and the drain of FET P2 is connected to conductor 5 to provide a path for input current, respectively, when the potential on AC1 is positive and when AC2 is positive. As is conventional with field effect transistor devices, the body and source are connected, and in circuit 1 the body of FET P1 is connected to the source of FET P1 via conductor 7 and similarly the body of FET P2 is connected to the source of FET P2 by conductor 8. Anode 9 of diode D1 is connected to output terminal 3 via conductor 10 and cathode 11 of diode D1 is connected to conductor 4. Diode D2 is connected between conductor 5 and conductor 10, with anode 12 being connected to conductor 10 and cathode 13 being connected to conductor 5. Filter capacitor C.sub.f has one plate connected to conductor 6 and its other plate connected to conductor 10 and resistor RL (which represents the load for full wave rectifier 1) is also connected between conductor 6 and conductor 10. Also included in full wave rectifier 1 is voltage clamp 14 which is connected between conductor 6 and conductor 10 and functions to shunt excess current away from load resistor RL in the presence of large input signals to limit the peak output voltage to a level below the breakdown voltage for the devices connected to conductors 6 and 10. Voltage clamp 14 may typically be a Zener diode or other suitable device which will accomplish the current shunting function.
The above noted problems with the typical prior art circuit, such as circuit 1, at startup and with overvoltage, will be illustrated with respect to a one-half cycle operation, illustrated in FIG. 2, which shows the conduction when the potential at input terminal AC1 is positive with respect to the potential at input terminal AC2. The first problem of startup occurs when filter capacitor C.sub.f is discharged and the output voltage between terminals 2 and 3 is zero. During the cycle of conduction in which AC1 is positive with respect to AC2, current flows from input terminal AC1 through FET P1, filter capacitor C.sub.f, diode D2 and back to input terminal AC2. At startup, the drive to turn on FET P1 (V.sub.GS) is provided by the voltage difference between input terminal AC1 and AC2. With no charge on filter capacitor C.sub.f, the drive voltage V.sub.GS to FET P1 will be limited to the voltage drop across diode D2 which is not sufficient to turn on FET P1, and this results in the drain to body diode forward biasing. The forward biased drain to body diode of FET P1 turns on the parasitic bipolar device inherent in FET P1, which results in the injection of large currents into the substrate which can cause the latch-up of other devices on the same substrate, resulting in the destruction of those devices.
The second limitation of prior art circuit 1 occurs when voltage clamp 14 is used to shunt excess current from load RL. To avoid large substrate currents with voltage clamp 14 in place, the peak AC input current to terminals AC1 and AC2 must not exceed a magnitude which causes the input current I.sub.p times the "on" resistance of FET P1 to exceed 0.6 volts. This voltage turns on the drain to body diode and injects current into the substrate through the parasitic bipolar device in the same manner as described above. For full wave rectifier circuit 1, the "on" resistance of FETs P1 and P2 is limited by the finite switch drive (V.sub.GS) determined by the voltage across clamp 14. It will of course be appreciated that the analogous problem results with FET P2 during the cycle in which the voltage at AC2 is positive with respect to the voltage at AC1.
From the foregoing it will be appreciated that the prior art presents the problems of injecting current into the substrate, which when the substrate is common with that used for other devices can destroy such devices; and in addition, because of the parasitic bipolar device inherent with the FETs the rectifier circuit is slow at startup in providing output DC potential because of the shunting of current around the load and filter capacitor.